Many computing systems, including but not limited to system-on-chips (SoCs) or other very-large-scale integration (VLSI) systems, implement queue-based processing of data packets and/or computing tasks. According to this technique, data packets or tasks generated by an application executed by the computing system are placed in one or more receive queues for processing by the computing system's central processing unit (CPU). The CPU processes the data packets or tasks for each receive queue in the order in which the packets were placed in the queue, and sends processed output data packets (e.g., processing results, acknowledgements, etc.) to one or more transmit queues for delivery to other system components (e.g., peripherals, output devices, storage locations in memory, etc.).
When new data is to be processed, computing systems typically generate an interrupt signal informing the CPU that new data is present in the receive queue and instructing the CPU to process this new data. The CPU responds to such interrupt signals by temporarily suspending one or more current processing activities in order to process the queued data.
In some scenarios, an interrupt signal is generated each time a new data packet or task is added to a receive queue. Since this approach can result in a large number of CPU interrupts, potentially degrading performance, some systems support interrupt coalescing, whereby the system delays generation of the interrupt signal upon receipt of a new data packet, allowing multiple data packets to accumulate in the receive queue before generating the interrupt. When the interrupt signal is generated in this scenario, the CPU processes multiple queued data packets during the same interrupt rather than processing only a single data packet per interrupt.
The above-described description is merely intended to provide a contextual overview of current techniques and is not intended to be exhaustive.